Continued development and upgrading of magnetic disk subsystems lead to the desirable features of higher performance, greater capacity, higher reliability, more connectivity, in addition to reduced power consumption, reduced footprint area, and reduced heat dissipation.
As seen in FIG. 1B, the general block diagram of the present mass storage and retrieval system would include a host processor 4 for several interface modules such as channel interface module 8.sub.c (CIM) and device interface module 8.sub.d (DIM) connected to a plurality of disk drive units 70 or other types of peripheral storage devices. The particular interfaces in various types of mass storage systems will vary according to the individual design of the manufacturer. In the present described architecture, the interfaces involve two particularly efficient interfaces known as the channel interface module 8.sub.c which uses the later described buffer memory of the mass storage system and also a device interface module (DIM) 8.sub.d which also uses the herein described buffer memory system configuration.
In the prior art and other conventional memory systems, where buffer memories were used in interfaces for Read, Write, and other operations in mass storage systems, the requirement of time multiplexing of the memory caused undesirable wait periods for accessing by the numerous sources which had to access the memory.
As an example, buffer memories would normally be accessed by various sources such as a host processor, a control processor, and by various data channels which communicated to a series of peripheral storage units. It was the problem of delay and of waiting for taking of turns for each of these particular outlying sources in accessing the buffer memory, that created and caused unacceptable delays.
When dual port buffer memories were used, this not only increased the cost, the amount of board surface involved, but also increased power usage on the board in addition to causing contention between the two ports of each memory. Even in this case, there were two sources of access which still had to wait for their turn for memory access and attention.
In order to reduce the use of power consumption and to reduce the amount of board surface required and especially to keep the simplicity as well as the n"fairness of access" to all of the sources available, the present architecture for a storage and retrieval system providing massive data storage having rapid access and retrieval on a simultaneous and concurrent basis using multiple peripheral storage devices, has been designed to overcome the aforementioned limitations. Further, redundancy of buses, power supplies and faulty module replacement without shutdown, allows uninterruptible access to stored information.